The present invention relates to semiconductor memory devices, and in particular, the invention relates to an architecture and package orientation for semiconductor memory devices.
Various arrangements have been proposed for increasing the speed of memory devices requiring high speed data throughput such as synchronous dynamic random access memory (SDRAM). Most of these arrangements have been directed to minimizing the access time for accessing the memory array. These arrangements include development of faster operating modes, such as extended data output mode, burst write and read modes, etc., and the use of pipelining arrangements. At the present time for example, the standard high Speed for known SDRAM devices is about 100 MHZ.
Although many exsisting memory devices provide fast operation, the extent to which speed can be increased is limited by the architecture and packaging of the memory device. For example, SDRAM devices are housed in packages that have an industry-standard pin layout and are of specified lengths and widths. Typically, SDRAM devices are contained in small outline-J lead (SOJ) packages. For a dual 1 Megxc3x974 SDRAM device, the width of the SOJ package is about 300 mils and the width of the thin, small outline package (TSOP) is about 400 mils. To make the chip on which the memory device is fabricated fit in such standard package, semiconductor manufactures orient the chip lengthwise within the package.
FIG. 1, which is labeled Prior Art, is a representation of the chip layout for a known dual bank SDRAM device 100 fabricated on a memory chip 102. The SDRAM device includes a bank 0 memory array 104 which extends along one side of the memory chip and a bank 1 memory array 106 which extends along the opposite side of the memory chip. Each memory array, such as memory array 104, includes a plurality of sub-arrays 105 having access circuitry including row decoder circuits, column decoder circuits and sense amplifier circuits. The row decoder circuits include row decoder circuits 107 which extend along the side 108 of the memory sub-arrays, row decoder circuits 109 which extend along the opposite side 110 of the sub-arrays, and row decoder circuits 111 which are located between the sub-arrays. The column decoder circuits 112 extend along one end 114 of the memory array near the one edge 116 of the memory chip 102. The sense amplifier circuits 118 are located between each of the sub-arrays of the memory array. Column select lines, such as column select lines 120 represented by dashed lines, extend through the memory array 104 om the column decoder circuits 112 at end 114 of the memory array 104 near edge 116 of the memory chip to the opposite end 122 of the memory array near the opposite edge 124 of the memory chip.
The data output register 128 is located adjacent to the edge 124 of the memory chip so as to be adjacent to the chip bond pads as is conventional. The memory chip includes a first plurality of chip bond pads 130 which are located along edge 116 of the memory chip and which provide connections to address inputs for the memory chip. A second plurality of chip bond pads 132, which are located along the opposite edge 124 of the memory chip, provide connections to data inputs/outputs for the memory chip. The memory further includes clock chip bond pads located along edge 116 of the memory chip, and power chip bond pads located along both edges 116, 124 of the memory chip.
FIG. 2, which is labeled xe2x80x9cPrior Artxe2x80x9d is a bond drawing for the known SDRAM device shown in FIG. 1 mounted in a package 202. By way of example, the package is a forty-four pin, thin small outline package (TSOP). As is shown in FIG. 2, the memory chip 102 is oriented lengthwise within the package in the conventional manner with the major axis of the memory chip extending along or parallel to the major axis of the package as is illustrated in FIG. 2. The package includes address pins A0-A3, A10 and BA, which extend along one side 204 of the package near one end 206 thereof and address input pins A4-A9 which extend along the opposite side 208 of the package near end 206. The package additionally includes data pins DQ0-DQ3 which extend along side 204 of the package near the opposite end 210 of the package, and data pins DQ4-DQ7 which extend along side 208 of the package near end 210. Also shown in FIG. 2 are the address chip bond pads 130 and the data chip bond pads 132. The address chip bond pads 130 are connected to the address pins A0-A10 and BA of the package in the conventional manner as represented by the dashed lines 212 and brackets. The data chip bond pads 132 are connected to the data pins DQ0-DQ7 in the conventional manner as represented by the dashed lines 214 and brackets. The package includes further pins, such as clock and timing signal input pins CLK, CKE, DQM, RAS*, CAS*, WE* and CS*, that are connected to corresponding clock chip bond pads and power input pins, such as power input pins VCC, VSS, VSSQ and VCCQ, that are connected to corresponding power chip bond pads. To simplify the drawings, only the address chip bond pads 130 and the data chip bond pads 132 are shown connected to the address pins and the data pins, respectively, of the package.
In conventional memory packages, the memory chip is oriented lengthwise within the package, as is illustrated in FIG. 2, so that the address chip bond pads are located adjacent to the address pins A0-A10 near one end 206 of the standard package, with some of the address pins located at one side of the package and the rest of the address pins located at the opposite side of the package. Also, the data chip bond pads are located adjacent to the data pins DQ0-DQ7 near the opposite end 210 of the standard page, with some of the data pins located at one side of the package and the rest of the data pins located at the opposite side of the package.
However, the orientation of the memory chip within the package dictates the locations of the access circuits. In conventional circuits, this requires that different portions of the memory access circuits be located on opposite sides of the chip. Conventionally, for each memory array, the column address circuitry 112 (FIG. 1) is located at one end 114 of the memory array and the data output register 128 is located at the opposite end 116 of the memory array. This layout requires that the column select lines, such as column select lines 120 (FIG. 1), run substantially the entire extent of the memory array from one end 114 to the opposite end 122 thereof, which introduces propagation delay into the data input/output path. Additional propagation delay is introduced by the data read/write lines 134 (FIG. 1) that connect the output of the sense amplifier circuits 118 to the data output register 128 because the data output register is located adjacent to the chip data bond pads 132 and is thus physically spaced apart from the data outputs of the memory arrays. The full length runs that are required for the column select lines and the data read/write lines dictate a high RC (resistor and capacitor) time constant for the column select lines and the data read/write lines which significantly impacts the operating time for the memory access circuits.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved architecture and package orientation for memory devices that speed up the operation of the memory device.
The present invention provides an architecture and package orientation for semiconductor memory devices, such as synchronous dynamic random access memory devices, which results in an increase in the operating speed of the memory devices.
In accordance with the invention, the memory chip is mounted in the package with its major axis directed along the minor axis of the package. In one embodiment in which the memory chip includes first and second memory banks or arrays, the data output register and the chip bond pads are located between the two memory arrays. The data read/write lines extend from sub-arrays of the memory array to the data output register. All of the address chip bond pads are located in one row and all of the data chip bond pads are located in another row that extends in parallel with the row of address chip bond pads.
In accordance with another aspect of the invention, the column decoder circuit for each memory array is located at the center of the memory array. This allows the column select lines to be segmented into two groups, with one group of column select lines extending from the center of the memory array outwardly toward one side of the memory array and with the other group of column select lines extending from the center of the memory array outwardly toward an opposite side of the memory array.
The memory architecture and layout provided by the invention reduces the length of the column select lines, with an attendant reduction in the RC (resistor and capacitor) time constant due to the resistance and capacitance of the column select lines so that memory access times can be reduced Moreover, minimizing the length of the data read/write lines reduces the data input/output path and further increases the speed of the memory device.